1. Field of the Invention
The invention relates, in general, to flash memory devices and, more particularly, to a method of forming a gate of a flash memory device.
2. Discussion of Related Art
As the level of integration of flash memory devices increases, a metal line formation method using the damascene method instead of the conventional Reactive Ion Etching (RIE) method is increasingly used. This is because in memory devices of 60 nm or less, a tungsten gate has a narrow width of 60 nm or less and is difficult to pattern using the conventional RIE method. In the case where a tungsten silicide (WSi) gate is used, it is difficult to secure a gate line. In the case where a target is increased so as to secure resistance, it results in increased intra-capacitance. Furthermore, a hard mask layer, a tungsten silicide layer, a polysilicon layer, and an oxide layer must be etched at the same time even at the time of gate etch. In the case where a tungsten gate is formed using the RIE method, it is difficult to form a spacer because of tungsten oxidization and the reliability of the gate is low due to thermal budget. In addition, in the case where the conventional tungsten (W) single damascene method is used, a first polysilicon layer pattern must be formed at the ISO level and the coupling ratio is decreased due to misalignment.